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| PRELIMINARY Integrated Circuit Systems, Inc. ICS8543 LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER FEATURES * 4 LVDS outputs * Designed to meet or exceed the requirements of ANSI TIA/EIA-644 * Selectable differential HSTL or LVPECL clock inputs * LVCMOS / LVTTL control inputs * 3.3V operating supply * 20 lead TSSOP * 0C to 70C ambient operating temperature GENERAL DESCRIPTION The ICS8543 is a low skew, high performance 1-to-4 clock fanout buffer and a member of HiPerClockSTM the HiPerClockSTM family of High Performance Clock Solutions from ICS. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8543 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100. The ICS8543 accepts any differential input level and translates it to 3.3V LVDS output levels. ,&6 Guaranteed output and part-to-part skew characteristics make the ICS8543 ideal for those applications demanding well defined performance and repeatability. BLOCK DIAGRAM CLK_EN nD Q LE HCLK nHCLK PCLK nPCLK 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 PIN ASSIGNMENT VEE CLK_EN CLK_SEL HCLK nHCLK PCLK nPCLK OE VEE VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VDD Q1 nQ1 Q2 nQ2 VEE Q3 nQ3 CLK_SEL ICS8543 20-Lead TSSOP G Package Top View OE The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. ICS8543BG www.icst.com/products/hiperclocks.html REV. C MAY 21, 2001 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS8543 LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER Type Power Input Pullup Description Power supply ground. Connect to ground. Synchronous clock enable. When HIGH clock outputs follows clock input. When LOW, Q outputs are force low, nQ outputs are force high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH selects differential PECL inputs. When LOW selects differential HSTL inputs. LVCMOS / LVTTL interface levels. Non-inver ting differential HSTL clock input. Inver ting differential HSTL clock input. Non-inver ting differential PECL clock input. Inver ting differential PECL clock input. Output enable. Controls enabling and disabling of outputs Q0, nQ0 thru Q3, nQ3 Power supply pin. Connect to 3.3V. Differential clock outputs. LVDS interface levels. Differential clock outputs. LVDS interface levels. Differential clock outputs. LVDS interface levels. Differential clock outputs. LVDS interface levels. TABLE 1. PIN DESCRIPTIONS Number 1, 9, 13 2 Name VEE CLK_EN 3 4 5 6 7 8 10, 18 11, 12 14, 15 16, 17 19, 20 CLK_SEL HCLK nHCLK PCLK nPCLK OE VDD nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 Input Input Input Input Input Input Power Output Output Output Output Pulldown Pulldown Pullup Pulldown Pullup Pullup TABLE 2. PIN CHARACTERISTICS Symbol Parameter HCLK, nHCLK CIN PCLK, nPLCK CLK_EN, CLK_SEL Input Pullup Resistor Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical Maximum 4 4 4 51 51 Units pF pF pF K K RPULLUP RPULLDOWN ICS8543BG www.icst.com/products/hiperclocks.html 2 REV. C MAY 21, 2001 PRELIMINARY Integrated Circuit Systems, Inc. ICS8543 LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER Outputs CLK_SEL X 0 1 0 Q1 thru Q3 Hi Z Low Low ACTIVE nQ1 thru nQ3 Hi Z High High ACTIVE TABLE 3A. CONTROL INPUTS FUNCTION TABLE Inputs OE 0 1 1 1 CLK_EN X 0 0 1 1 1 1 ACTIVE ACTIVE In the active mode the state of the output is a function of the HCLK, nHCLK and PCLK, nPCLK inputs as described in Table 3B. TABLE 3B. CLOCK INPUTS FUNCTION TABLE Inputs HCLK, PCLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nHCLK, nPCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Outputs Input to Output Mode Q0 thru Q3 LOW HIGH LOW HIGH HIGH LOW nQ0 thru nQ3 HIGH LOW HIGH LOW LOW HIGH Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting Polarity NOTE 1: Single ended use requires that one of the differential inputs be biased. The voltage at the biased input sets the switch point for the single ended input. For LVCMOS and LVTTL levels the recommended input bias network is a resistor to VCC, a resistor of equal value to ground and a 0.1F capacitor from the input to ground. The resulting switch point is approximately VCC/2 300mV. ICS8543BG www.icst.com/products/hiperclocks.html 3 REV. C MAY 21, 2001 PRELIMINARY Integrated Circuit Systems, Inc. ICS8543 LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER 4.6V -0.5V to VDD + 0.5V -0.5V to VDD + 0.5V 0C to 70C -65C to 150C ABSOLUTE MAXIMUM RATINGS Supply Voltage Inputs Outputs Ambient Operating Temperature Storage Temperature Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, TA=0C TO 70C Symbol VDD IEE Parameter Power Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 50 Units V mA TABLE 4B. LVPECL DC CHARACTERISTICS, VDD = 3.3V5%, TA=0C TO 70C Symbol IIH IIL VPP VCMR Parameter Input High Current Input Low Current PCLK nPCLK PCLK nPCLK -5 -150 0.15 1.5 1.3 3.3 Test Conditions Minimum Typical Maximum 150 5 Units A A A A V V Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1 NOTE 1: Common mode voltage for LVPECL is defined as the minimum VIH. TABLE 4C. LVHSTL DC CHARACTERISTICS, VDD = 3.3V5%, TA=0C TO 70C Symbol IIH IIL VPP Parameter Input High Current Input Low Current HCLK nHCLK HCLK nHCLK Test Conditions 3.135V VDDI 3.465V 3.135V VDDI 3.465V 3.135V VDDI 3.465V 3.135V VDDI 3.465V -5 -150 0.15 1.3 Minimum Typical Maximum 150 5 Units A A A A V Peak-to-Peak Input Voltage VCMR Common Mode Input Voltage; NOTE 1 0.5 VDD - 0.85 V NOTE 1: Common mode voltage for HSTL is defined as the crossover voltage. VCMR is compatible with DCM, LVDS and SSTL inputs. ICS8543BG www.icst.com/products/hiperclocks.html 4 REV. C MAY 21, 2001 PRELIMINARY Integrated Circuit Systems, Inc. ICS8543 LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER Test Conditions CLK_EN, CLK_SEL, OE CLK_EN, CLK_SEL, OE CLK_EN, OE CLK_SEL CLK_EN, OE CLK_SEL -150 -5 Minimum 2 0.8 5 150 Typical Maximum Units V V A A A A TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, TA=0C TO 70C Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current TABLE 4E. LVDS DC CHARACTERISTICS, VDD = 3.3V5%, TA=0C TO 70C Symbol VOD VOD VOS VOS IOZ IOFF IOSD IOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change High Impedance Leakage Current Power Off Leakage Differential Output Shor t Circuit Current Output Shor t Circuit Current -10 -20 1.125 Test Conditions Minimum 250 Typical 350 4 1.25 5 1 1 3.0 3.0 Maximum 450 35 1.375 25 +10 +20 Units mV mV V mV A A mA mA TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, TA=0C TO 70C Symbol fMAX tpLH tsk(o) tsk(pp) tR tF tPW tEN Parameter Maximum Input Frequency Propagation Delay, Low-to-High Output Skew; NOTE 2 Par t-to-Par t Skew; NOTE 3 Output Rise Time Output Fall Time Output Pulse Width Output Enable Time RL = 100 RL = 100 200 200 tCYCLE/2 - TBD 400 400 0 f 650MHz 1.8 Test Conditions Minimum Typical Maximum 650 2.4 50 300 600 600 tCYCLE/2 + TBD TBD Units MHz ns ps ps ps ps ns ns ns tDIS Output Disable Time TBD NOTE 1: All parameters measured at fMAX unless noted otherwise. NOTE 2: Defined as skew across outputs at the same supply voltages and with equal load conditions. Measured from the 50% point of the input to the differential output crossing point. NOTE 3: Defined as skew at different outputs on different devices operating at the same supply voltages and with equal load conditions. Measured from 50% of like inputs to the differential output crossing point. ICS8543BG www.icst.com/products/hiperclocks.html 5 REV. C MAY 21, 2001 PRELIMINARY Integrated Circuit Systems, Inc. ICS8543 LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER PACKAGE OUTLINE - G SUFFIX N c 20 11 L E1 E 1 10 D A2 A -Ce b A1 SEATING PLANE aaa C TABLE 6. PACKAGE DIMENSIONS SYMBOL MIN N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 1.20 0.15 1.05 0.30 0.20 6.60 Millimeters MAX 20 -0.002 0.032 0.007 0.0035 0.252 0.047 0.006 0.041 0.012 0.008 0.260 MIN Inches MAX 0.252 BASIC 0.169 0.177 0.0256 BASIC 0.018 0 -0.030 8 0.004 Reference Document: JEDEC Publication 95, MO-153 ICS8543BG www.icst.com/products/hiperclocks.html 6 REV. C MAY 21, 2001 PRELIMINARY Integrated Circuit Systems, Inc. ICS8543 LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER Marking Package 20 lead TSSOP 20 lead TSSOP on Tape and Reel Count 72 per tube 2500 Temperature 0C to 70C 0C to 70C TABLE 7. ORDERING INFORMATION Part/Order Number ICS8543BG ICS8543BGT ICS8543BG ICS8543BG While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. ICS8543BG www.icst.com/products/hiperclocks.html 7 REV. C MAY 21, 2001 |
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